This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-300491, filed on Sep. 29, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a liquid crystal driving circuit in which grayscale display is possible, and a load driving circuit for selectively driving a capacitive load.
2. Related Background Art
Since there is only a limited space in a cellular phone, a large-capacitance battery cannot be mounted, and power consumption of a circuit in the phone needs to be reduced as much as possible. On the other hand, a cellular phone having a color liquid crystal panel has increased.
A conventional source driver IC for driving a liquid crystal panel has a buffer amplifier for each signal line in the panel. Therefore, the source driver IC having m pieces of driving output terminals always operate m (e.g., 384 or 420) pieces of buffer amplifiers, thereby increasing the power consumption.
FIG. 11 is a block diagram showing a schematic configuration of this type of conventional signal line driving circuit. The signal line driving circuit of FIG. 11 includes: a shift register 1 for successively shifting a shift pulse supplied from the outside in synchronization with a transfer clock; a plurality of data latch circuits 2 for latching digital grayscale data in synchronization with the shift pulse outputted from each output terminal of the shift register 1; a load latch circuit 3 for latching outputs of the plurality of data latch circuits 2 at the same timing; a level shifter 4 for converting a level of an output of the load latch circuit 3; a D/A converter 5 for outputting an analog voltage in accordance with an output of the level shifter 4; a buffer amplifier 6 for buffering an output of the D/A converter 5; and a breeder 7 for generating an analog reference voltage corresponding to the digital grayscale data. Each output of the buffer amplifier 6 is supplied to each signal line.
Briefly, the breeder 7 divides an external voltage between two power supply voltage (Vcc and GND) by a plurality of resistors connected in series and generates the analog reference voltage.
In the conventional signal line driving circuit shown in FIG. 11, as one method for solving a problem that the power consumption increases, there is proposed a method of disposing the buffer amplifier for each reference voltage line for supplying the analog reference voltage, instead of disposing the buffer amplifier for each signal line. In this case, when the number of grayscales is n, 2n pieces of buffer amplifiers may be disposed. As compared with the buffer amplifiers disposed for the respective signal lines, the number of buffer amplifiers can largely be reduced, and the power consumption can be reduced.
FIG. 12 is a block diagram of a display apparatus disclosed in Japanese Patent Application Laid-Open No. 326084/1998, in which the buffer amplifier is disposed for each reference voltage line. The display apparatus of FIG. 12 includes switches SW10 to SW25 for switching whether or not to operate each buffer amplifier, and a grayscale conversion/buffer control circuit 71 for selecting a grayscale number in accordance with an input image signal. The number of buffer amplifiers to be operated is changed in accordance with the selected grayscale number, thereby reducing the power consumption.
However, since the display apparatus of FIG. 12 always selects the grayscale number in accordance with the input image signal, a processing burden in the grayscale conversion/buffer control circuit 71 increases. Particularly, when the input image signal frequently changes, e.g. a moving picture, the power consumption of the grayscale conversion/buffer control circuit 71 possibly increases. Moreover, a memory for storing at least one frame of input image signals is necessary, and it is difficult to miniaturize the circuit. Furthermore, the display apparatus of FIG. 12 converts the inputted analog image signal by an A/D converter 72, and then carries out the processing in the grayscale conversion/buffer control circuit 71. Therefore, a high-precision A/D converter is required, thereby increasing a component cost.
For example, when the cellular phone is in a waiting state, only minimum information such as a character is preferably displayed to suppress the power consumption as much as possible. However, when the display apparatus of FIG. 12 is used for the cellular phone, the power consumption of the grayscale conversion/buffer control circuit 71 does not decrease even in the waiting state, and as a result, a waiting time is shortened.
When the buffer amplifier 6 is disposed for each reference voltage line for supplying the analog reference voltage as shown in FIG. 11, it is general to constitute the buffer amplifier 6 by an operational amplifier 11 including two gain stages. Moreover, to improve stability, as shown in FIG. 13A, an output terminal of the output gain stage 11 is fed back to an input terminal via a capacitor element C10, and a phase margin is secured by Miller compensation. Alternatively, as shown in a circuit of FIG. 14A proposed in Japanese Patent Application Laid-Open No. 150427/1999, the phase margin is secured by performing phase compensation using a zero obtained by a resistance Rz and load capacitance CL connected in series to the output.
In the circuit of FIG. 13A, a second pole appearing in an open loop frequency characteristic depends on a frequency gm2/CL determined by a transconductance gm2 of a second gain stage and the load capacitance CL as shown in a frequency characteristic diagram of FIG. 13B. Additionally, a phase rotates by 90 degrees per pole.
In the circuit of FIG. 13A, the larger the load capacitance becomes, the lower the frequency of the second pole becomes, i.e. gm2/(mxc2x7CL), in accordance with the number m of loads to be driven. Therefore, even in case of a small load capacitance, the phase margin is reduced in driving m (m greater than  greater than 1) loads. When m is larger, there is a problem that the phase margin is further reduced, and oscillation easily occurs.
On the other hand, in the circuit of FIG. 14A, as shown in a frequency characteristic diagram of FIG. 14B, even when a load amount changes, the frequency of the second pole does not move. However, the frequencies of the first pole and the zero change in accordance with the load amount. Moreover, in the circuit of FIG. 14A, as the number of loads increases, a waveform becomes more dull and a settling time becomes longer by a low pass characteristic due to the resistance Rz and load capacitance mxc2x7CL.
According to the present invention, there is provided a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising:
a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data;
a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages;
a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and
an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.
Moreover, according to the present invention, there is provided a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising:
a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data;
a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages;
a grayscale data use judgment circuit configured to check grayscale inputted at least once or more based on said digital grayscale data inputted within a predetermined period; and
an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output of said grayscale data use judgment circuit.
Furthermore, according to the present invention, there is provided a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising:
a reference voltage generation circuit configured to output an analog reference voltage corresponding to each of said digital grayscale data;
a shift register configured to output a shift pulse obtained by successively shifting a pulse signal;
a plurality of first latch circuits configured to latch said digital grayscale data in synchronization with the shift pulse outputted from each output terminal of said shift register;
a second latch circuit configured to latch respective outputs of said plurality of first latch circuits substantially at the same timing;
a decoder configured to generate a decode signal based on an output of said second latch circuit;
an output selection circuit configured to output a desired analog voltage for each of said plurality of signal lines based on an output of said decoder; and
a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside,
wherein each of said first latch circuits comprises at least latch sections corresponding to a maximum grayscale number, and
the number of said latch sections brought to an enable state is set to be variable based on an output signal of said grayscale mode signal.
Additionally, there is provided a load driving circuit configured to selectively drive m (m being an integer of 1 or more) pieces of loads based on an output of an operational amplifier, said circuit comprising:
a switch configured to switch whether or not a connection path between each of said loads and said operational amplifier is to be cut; and
impedance elements connected to respective paths extended to said m pieces of loads from an output terminal of said operational amplifier through said switch.
Moreover, there is provided a load driving circuit configured to selectively drive m (m being an integer of 1 or more) pieces of loads based on an output of an operational amplifier, said circuit comprising:
a switch configured to switch whether or not a connection path between each of said loads and said operational amplifier is to be interrupted;
impedance elements connected to respective paths extended to said m pieces of loads from an output terminal of said operational amplifier through said switch; and
a pseudo impedance element, a pseudo switch and a pseudo capacitor element connected in series to the output terminal of said operational amplifier,
wherein a product of an impedance of said pseudo impedance element and a capacitance of said pseudo capacitor element is almost equal to a product of the impedance of said impedance element and the capacitance of said load.